8S89833 Datasheet, PDF (2/17 Pages) Integrated Device Technology – Low Skew, 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination

8S89833 Data Sheet
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, nQ0
3, 4
Q1, nQ1
5, 6
7, 14
8
9
10
11
12
13
15, 16
Q2, nQ2
V_DD
EN
nIN
V_{REF_AC}
V_T
IN
GND
Q3, nQ3
Type
Output
Output
Output
Power
Input
Input
Output
Pullup
Input
Input
Power
Output
Description
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
Power supply pins.
Synchronizing output enable pin. When LOW, disables outputs. When HIGH, enables
outputs. Internally connected to a 37k pullup resistor. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50 termination to V_T.
Reference voltage for AC-coupled applications. Equal to V_DD - 1.4V (approx.). Maximum
sink/source current is ±2mA.
Input termination center-tap. Each side of the differential input pair terminates to a V_T pin.
The V_T pins provide a center-tap to a termination network for maximum interface flexibility.
Non-inverting differential clock input. RT = 50 termination to V_T.
Power supply ground.
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
R_PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
©2016 Integrated Device Technology, Inc
2
Revision B August 24, 2016