843204I-01 Datasheet, PDF (2/14 Pages) Integrated Device Technology – FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer

843204I-01 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
nQA1, QA1
Output
Differential output pair. LVPECL interface levels.
3, 4
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
5, 10, 11, 12,
13, 20, 25, 26,
27, 28, 29, 37,
44
nc
Unused
No connect.
6
V
Power
Output supply pin for Bank A outputs.
CCO_A
7
SELA1
Input
Pulldown
Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. When LOW,
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
8
SELA0
Input
Pulldown
Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. When LOW,
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
9
nPLL_BYPASS_A Input Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active.
14,
15
XTAL_IN1, XTAL_
OUT1
Input
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
16
CLK1
Input Pulldown Non-inverting differential clock input.
17
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. V /2 bias voltage when left floating.
DD
18
IN_SELB
Input
Pullup
Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects CLK1,
nCLK1 inputs. LVCMOS/LVTTL interface levels.
19
21, 22
V
CCO_B
QB0, nQB0
Power
Ouput
Output supply pin for Bank B outputs.
Differential output pair. LVPECL interface levels.
23, 24
QB1, nQB1
Ouput
Differential output pair. LVPECL interface levels.
30, 39
31
V
CCA
SELB1
Power
Input
Pullup
Analog supply pins.
Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW,
selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels.
32, 40
33
V
CC
OEB1
Power
Input
Pullup
Core supply pins.
Output enable pin. QB1/nQB1 outputs are enable.
LVCMOS/LVTTL interface levels.
34
OEB0
Input
Pullup
Output enable pin. QB0/nQB0 outputs are enabled.
LVCMOS/LVTTL interface levels.
35, 43
36
V
EE
SELB0
Power
Input
Pullup
Negative supply pins.
Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW,
selects QB0/nQB0 at 156.25MHz. LVCMOS/LVTTL interface levels.
38
nPLL_BYPASS_B Input Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active.
41
OEA1
Input
Pullup
Output enable pin. QA1/nQA1 outpus are enabled.
LVCMOS/LVTTL interface levels.
42
OEA0
Input
Pullup
Output enable pin. QA0/nQA0 outputs are enabled.
LVCMOS/LVTTL interface levels.
45,
46
XTAL_OUT0,
XTAL_IN0
Input
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
47
CLK0
Input Pulldown LVCMOS/LVTTL clock input.
48
IN_SELA
Input
Pullup
Select pin. When HIGH, selects XTAL0 inputs. When LOW, selects CLK0
input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C
IN
R
PULLDOWN
R
PULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions
2
Minimum
Typical
4
51
51
Maximum Units
pF
k
Ω
k
Ω
REVISION A 11/5/15