83947 Datasheet, PDF (2/10 Pages) Integrated Device Technology – Maximum output frequency

83947 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32
GND
Power
Power supply ground.
2
CLK_SEL
Input
Pullup
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
3, 4
CLK0, CLK1
Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
5
CLK_EN
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
6
OE
Input Pullup Output enable. LVCMOS / LVTTL interface levels.
7
10, 14, 18, 22, 27, 31
11, 13, 15, 19, 21, 23,
26, 28, 30
V_DD
Power
V_DDO
Power
Q8, Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Coree supply pin.
Output supply pins.
Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
C_PD
R_PULLUP
R_PULLDOWN
R_OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum Typical Maximum Units
4
pF
25
pF
51
KΩ
51
KΩ
5
7
12
Ω
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
OE
CLK_EN
0
X
1
0
1
1
Output
Q0:Q8
Hi-Z
LOW
Follows CLK input
LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER
2
REVISION B 11/10/14