83054_15 Datasheet, PDF (2/14 Pages) Integrated Device Technology – 4:1, Single-Ended Multiplexer

83054 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
3
4, 8,
10, 14
OE
CLK3, CLK2,
CLK1, CLK0
Input
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
5
GND
Power
Power supply ground.
7, 9
SEL1, SEL0
Input
Pulldown
Clock select input. See Control Input Function Table.
LVCMOS / LVTTL interface levels.
2, 6, 11, 13, 15
nc
Unused
No connect.
12
V
Power
Power and input supply pin.
DD
16
V
Power
Output supply pin.
DDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
C
PD
Power Dissipation Capacitance
(per output)
R
Output Impedance
OUT
Test Conditions
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
Minimum
Typical
4
51
51
18
20
30
7
7
10
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs
SEL1
SEL0
0
0
0
1
1
0
1
1
Input Selected to Q
CLK0
CLK1
CLK2
CLK3
©2015 Integrated Device Technology, Inc
2
December 15, 2015