74FCT574T Datasheet, PDF (2/7 Pages) Integrated Device Technology – FAST CMOS OCTAL D REGISTERS (3-STATE)

IDT54/74FCT574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
PIN CONFIGURATION
OE 1
D0 2
D1
3
D2 4
D3
5
D4 6
D5
7
D6 8
D7
9
GND 10
20
VCC
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
11 ^CP
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
INDEX
32
20 19
D2
4
1
18
Q1
D3
5
17
Q2
D4
6
16
Q3
D5
7
15
Q4
D6
8
14
Q5
9 10 11 12 13
CERDIP/ SOIC/ TSSOP
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Symbol
Description
Max
Unit
VTERM⁽²⁾ Terminal Voltage with Respect to GND
–0.5 to +7
V
VTERM⁽³⁾ Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature
–65 to +150
°C
PIN DESCRIPTION
Pin Names
Description
Dx
D flip-flop data inputs
CP
Clock Pulse for the register. Enters data on LOW-to-
HIGH transition.
IOUT
DC Output Current
–60 to +120
mA
Qx
3-State Outputs (TRUE)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Qx
3-State Outputs (INVERTED)
OE
Active LOW 3-State Output Enable Input
FUNCTION TABLE⁽¹⁾
Inputs
Function
OE
CP
Dx
Outputs
Qx
Internal
Qx
High-Z
H
L
X
Z
NC
H
H
X
Z
NC
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Load
L
↑
L
L
H
Symbol
Parameter⁽¹⁾
CIN
Input Capacitance
Conditions Typ. Max. Unit
VIN = 0V
6
10 pF
Register
L
H
H
COUT
Output Capacitance VOUT = 0V
8
12 pF
NOTE:
↑
↑
↑
H
L
H
H
Z
Z
L
H
L
NOTE:
1. H = HIGH Voltage Level
1. This parameter is measured at characterization but not tested.
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH transition
2