5PB1102PGG Datasheet, PDF (2/21 Pages) Integrated Device Technology – 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family

5PB11xx DATASHEET
Pin Assignments for TSSOP Packages
CLKIN 1
1G 2
Y0 3
GND 4
5PB1102PGG
8 Y1
7 NC
6 VDD
5 NC
CLKIN 1
1G 2
Y0 3
GND 4
5PB1104PGG
8 Y1
7 Y3
6 VDD
5 Y2
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
5PB1106PGG
14 Y1
13 Y3
12 VDD
11 Y2
10 GND
9 Y5
8 VDD
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
5PB1108PGG
16 Y1
15 Y3
14 VDD
13 Y2
12 GND
11 Y5
10 VDD
9 Y7
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y9 10
5PB1110PGG
20 Y1
19 Y3
18 VDD
17 Y2
16 GND
15 Y5
14 VDD
13 Y7
12 Y8
11 GND
Pin Descriptions for TSSOP Packages
Device Number
5PB1102PGG
5PB1104PGG
5PB1106PGG
5PB1108PGG
5PB1110PGG
LVCMOS
Clock Input
CLKIN
1
1
1
1
1
Clock Output
Enable
LVCMOS Clock Output
1G
Y0, Y1, . . . Y9
2
3, 8
2
3, 8, 5, 7
2
3, 14, 11, 13, 6, 9
2
3, 16, 13, 15, 6, 11, 8, 9
2
3, 20, 17, 19, 6, 15, 8, 13, 12, 10
Supply Voltage
VDD
6
6
5, 8, 12
5, 10, 14
5, 9, 14, 18
Ground
GND
4
4
4, 7, 10
4, 7, 12
4, 7, 11, 16
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
2
MARCH 28, 2017