5P35021 Datasheet, PDF (2/34 Pages) Integrated Device Technology – VersaClock Programmable Clock Generator

5P35021 DATASHEET
Functional Block Diagram
OSC
CLKINB/X1
CLKIN/X2
PLL1
MUX
DIV1
DIV2
DIV1/REF
DIV3
MUX
DIV1/REF
DIV3
MUX
VBAT
VDD33
VDDA
VSS
SCL_DFC1
SDA_DFC0
Power
Monitor
POR
MUX
PLL2
MUX
DIV3
MUX
DIV4
Calibriation
32.768K
DCO
MUX
PLL3
DIV5
DIV4/REF
DIV5
32K
MUX
I2C Engine
Overshot Reduction
(ORT)
Dynamic Frequency Control Logic (DFC)
OTP memory (1 configuration)
Proactive Power Saving Logic (PPS)
Timer
Power Group
Power supply table
SE
DIFF
DIV
MUX
PLL DCO REF
Xtal
VDDSE1
SE1
VDDDIFF1
DIFF1 DIV3/4 MUXPLL2 PLL2
VDDDIFF2
DIFF2 DIV1 MUXPLL1
VDD33
DIV5
PLL3 DCO REF
Xtal
VBAT
DCO
Xtal
VDDA
DIV2
PLL1
* VDDSEx for non 32KHz outputs should be OFF when VDDA/VDD3 turn OFF, VBAT mode only support
32.768KHz outputs from SE1~3
* Vbat power ramp up should be same or earlier than other Vdd power rail
Output Source Table
Source:
Xtal REF
32.768KHz
PLL1
PLL2
PLL3
SE1
Xtal REF
32.768KHz
PLL2
PLL3
Outputs:
DIFF1
Xtal REF
PLL1
PLL2
PLL3
DIFF2
Xtal REF
PLL1
PLL2
PLL3
VDDDIFF2
DIFF2
DIFF2B
VDDDIFF1
DIFF1
DIFF1B
OE1
SE1
VDDSE1
VERSACLOCK^® PROGRAMMABLE CLOCK GENERATOR
2
SEPTEMBER 20, 2016