F2250NLGK Datasheet, PDF (19/24 Pages) Integrated Device Technology – Voltage Variable RF Attenuator

F2250NLGK
Datasheet
Voltage Variable RF Attenuator
50MHz to 6000MHz
APPLICATIONS INFORMATION
Default Start-up
VMODE must be tied to either GND or Logic HIGH. If VCTRL pin is left floating, the part will power up in the
minimum attenuation state when VMODE = GND, or the maximum attenuation state when VMODE = High.
VCTRL
The VCTRl pin is used to control the attenuation of the F2250. With VMODE set to a logic low (high) this places
the device in a negative (positive) slope mode where increasing (decreasing) voltage produces an increasing
(a decreasing) attenuation from min attenuation (max attenuation) to max attenuation (min attenuation)
respectively. The VCTRl pin has an on-chip pullup ESD diode so VDD should be applied before VCTRl is applied.
If this sequencing is not possible, then resistor R2 should be set for 1kΩ to limit the current into the VCTRL pin.
VMODE
The VMODE pin is used to set the attenuation vs. VCTRl slope. With VMODE set to logic low (high) this will set the
attenuation slope to be negative (positive). A negative (positive) slope is defined as increased (decreased)
attenuation with increasing (decreasing) VCTRl voltage. The EVKIT provides and on-board jumper to manually
set the VMODE. Installing a jumper on header J2 from VMODE to GND (VHI) to set the device for a negative
(positive) slope.
RF1 and RF2 Ports
The F2250 is a bi-directional device thus allowing RF1 or RF2 to be used as the RF input. As displayed in the
Typical Operating Conditions curves, RF1 shows some enhanced linearity performance and therefore should
be used as the RF input, if possible, for best results. This F2250 has been designed to accept high RF input
power levels, therefore VDD must be applied prior to the application of RF power to ensure reliability. DC
blocking capacitors are required on the RF pins and should be set to a value that results in a low reactance
over the frequency range of interest.
Power Supplies
The supply pin should be bypassed with external capacitors to minimize noise and fast transients. Supply noise
can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage
change or transients should have a slew rate smaller than 1V/20uS. In addition, all control pins should remain
at 0V (+/-0.3V) while the supply voltage ramps or while it returns to zero.
Voltage Variable RF Attenuator
19
REV 4, January 2017