SSTE32882KA1 Datasheet, PDF (18/75 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Symbol
Parameter
Signals
Min
Nom
Max
Unit
V_OX Differential Output Crosspoint Voltage (1.5V Operation)
Differential Output Crosspoint Voltage (1.35V Operation)
Yn, Yn
Yn, Yn
0.5xV_DD – 100 mV
–
0.5xV_DD + 100 mV V
0.5xV_DD – 90 mV
–
0.5xV_DD + 90 mV V
1 DCKE0/1, DODT0/1, DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE, PAR_IN, DCS[1:0] when QCSEN = HIGH, DCS[3:0] when QCSEN = LOW.
2 RESET, MIRROR
3 This spec applies only when both CK and CK are actively driven LOW. It does not apply when CK/CK are floating.
4 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-275 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns.
5 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns.
6 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 3.6 V/ns
7 VID is the magnitude of the difference between the input level on CK and the input level on CK See Diagram (Voltage waveforms; input clock)
8 Default settings
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
18
SSTE32882KA1
7314/9