IDTCV122C Datasheet, PDF (18/19 Pages) Integrated Device Technology – PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR

IDTCV122C
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD DE-ASSERTION
The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is
programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion.
PWRDWN
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tSTABLE <1.8mS
tDRIVE_PWRDWN
<300µS, <200mV
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