DAC1405D650 Datasheet, PDF (18/41 Pages) NXP Semiconductors – Dual 14-bit DAC, up to 650 Msps; 2´ 4´ and 8´ interpolating

Integrated Device Technology
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2, 4 and 8 interpolating
Table 11. TXCFG register (address 01h) bit description …continued
Default settings are shown highlighted.
Bit Symbol
Access Value Description
4 to 2 MODULATION[2:0] R/W
modulation
000
dual DAC: no modulation
001
positive upper single sideband
up-conversion
010
positive lower single sideband up-conversion
011
negative upper single sideband
up-conversion
100
negative lower single sideband up-conversion
1 to 0 INTERPOLATION[1:0] R/W
interpolation
01
2
10
4
11
8
Table 12. PLLCFG register (address 02h) bit description
Default settings are shown highlighted.
Bit Symbol
Access Value Description
7
PLL_PD
R/W
PLL
0
switched on
1
switched off
6
-
R/W
undefined
5
PLL_DIV_PD
R/W
PLL divider
0
switched on
1
switched off
4 to 3 PLL_DIV[1:0]
R/W
PLL divider factor
00
2
01
4
10
8
2 to 1 PLL_PHASE[1:0]
R/W
PLL phase shift of f_s
00
0
01
120
10
240
0
PLL_POL
R/W
clock edge of DAC (f_s)
0
normal
1
inverted
Table 13. FREQNCO_LSB register (address 03h) bit description
Bit Symbol
Access Value Description
7 to 0 FREQ_NCO[7:0]
R/W -
lower 8-bits for the NCO frequency setting
DAC1405D650 5
Product data sheet
Rev. 05 — 2 July 2012
© IDT 2012. All rights reserved.
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