8SLVP2104 Datasheet, PDF (18/23 Pages) Integrated Device Technology – Maximum input clock frequency

8SLVP2104 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
V_CC
Q1
V_OUT
RL
V_CC - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V_CC – 2V.
These are typical calculations.
• For logic high, V_OUT = V_{OH_MAX} = V_{CC_MAX} – 0.8V
(V_{CC_MAX} – V_{OH_MAX}) = 0.8V
• For logic low, V_OUT = V_{OL_MAX} = V_{CC_MAX} – 1.4V
(V_{CC_MAX} – V_{OL_MAX}) = 1.4V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V_{OH_MAX} – (V_{CC_MAX} – 2V))/R_L] * (V_{CC_MAX} – V_{OH_MAX}) = [(2V – (V_{CC_MAX} – V_{OH_MAX}))/R_L] * (V_{CC_MAX} – V_{OH_MAX}) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(V_{OL_MAX} – (V_{CC_MAX} – 2V))/R_L] * (V_{CC_MAX} – V_{OL_MAX}) = [(2V – (V_{CC_MAX} – V_{OL_MAX}))/R_L] * (V_{CC_MAX} – V_{OL_MAX}) =
[(2V – 1.4V)/50] * 1.4V = 16.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 36mW
LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT
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FANOUT BUFFER
REVISION C 6/8/15