IDT72V36100 Datasheet, PDF (17/48 Pages) Integrated Device Technology – 3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II^TM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
1st Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
8 765432
D/Q0
1
2nd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
16 15 14 13 12 11 10
D/Q0
9
3rd Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
87654 3 2
D/Q0
1
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
16 15 14 13 12 11 10
D/Q0
9
IDT72V36100 ⎯ x9 Bus Width
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1st Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
8 765432
D/Q0
1
2nd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
16 15 14 13 12 11 10
D/Q0
9
3rd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
D/Q0
17
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
8 7 654 3 2
D/Q0
1
5th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
16 15 14 13 12 11 10
D/Q0
9
6th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
D/Q0
17
IDT72V36110 ⎯ x9 Bus Width
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
6117 drw07a
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
17
APRIL 6, 2006