IDT72V285 Datasheet, PDF (17/25 Pages) Integrated Device Technology – 3.3 VOLT CMOS SuperSync FIFO

WCLK
WEN
D0 - D17
tENS
tDS
W1
RCLK
tDH
W2
tSKEW3⁽¹⁾
1
W3
2
REN
Q0 - Q17
OR
PAE
DATA IN OUTPUT REGISTER
1
tDS
tDS
tDS
W4
W[n +2]
W[n+3]
W[n+4]
W[^D-1 ] W[^D-1 ] W[^D-1 ] W[D-m-2]
W[D-m-1]
W[D-m]
W[D-m+1] W[D-m+2]
W[D-1]
WD
tSKEW2⁽²⁾
3
1
2
tA
W1
tREF
tPAE
tENH
HF
tHF
tPAF
PAF
IR
tWFF
4512 drw 12
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW3, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAE. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 32,769 for IDT72V275 and 65,537 for IDT72V285.
6. First word latency: 60ns + tREF + 2*TRCLK.
Figure 9. Write Timing (First Word Fall Through Mode)