IDT72V255LA_14 Datasheet, PDF (17/27 Pages) Integrated Device Technology – 3.3 VOLT CMOS SuperSync FIFO

IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
WCLK
D0 - Dn
t SKEW1 ⁽¹⁾
NO WRITE
1
t CLKH
2
t DS
t CLK
tCLKL
t DH
DX
t WFF
t WFF
(1)
t SKEW1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
1
2
t DS
t DH
t WFF
DX+1
t WFF
WEN
RCLK
REN
Q0 - Qn
t ENS
t ENH
tA
DATA IN OUTPUT REGISTER
t ENS
DATA READ
t ENH
tA
NEXT DATA READ
4672 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
RCLK
tENS
REN
EF
Q0 - Qn
OE
WCLK
WEN
D0 - Dn
tENH
tREF
1
NO OPERATION
tCLKH
2
NO OPERATION
tREF
tCLK
tCLKL
tENS
tENH
tA
tOLZ
tOE
tSKEW3⁽¹⁾
LAST WORD
tOHZ
tA
LAST WORD
tOLZ
tENS
tENH
tDS
D0
tDHS
tENS
tENH
tDS
tDH
D1
tENS
tENH
tREF
tA
D0
D1
4672 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: 60ns + tREF + 1*TRCLK.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
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