IDT70V639S Datasheet, PDF (17/23 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

IDT70V639S
High-Speed 3.3V 128K x 18 Asynchronous Dual-Port Static RAM
Waveform of Interrupt Timing⁽¹⁾
tWC
Preliminary
Industrial and Commercial Temperature Ranges
ADDR"A"
CE"A"
INTERRUPT SET ADDRESS⁽²⁾
tAS⁽³⁾
tWR ⁽⁴⁾
R/W"A"
INT"B"
tINS ⁽³⁾
ADDR"B"
CE"B"
tRC
INTERRUPT CLEAR ADDRESS ⁽²⁾
tAS ⁽³⁾
OE"B"
INT"B"
tINR ⁽³⁾
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5621 drw 16
5621 drw 17
Truth Table III — Interrupt Flag^(1,4)
Left Port
R/WL
CEL
OEL
A16L-A0L
INTL
R/WR
CER
L
L
X
1FFFF
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L⁽³⁾
L
L
X
L
L
1FFFE
H⁽²⁾
X
X
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
Right Port
OER
A16R-A0R
X
X
L
1FFFF
X
1FFFE
X
X
INTR
Function
L⁽²⁾ Set Right INTR Flag
H⁽³⁾ Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
5621 tbl 16
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