DT72281_13 Datasheet, PDF (17/26 Pages) Integrated Device Technology – CMOS SuperSync FIFO

IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
WCLK
D0 - Dn
t SKEW1 ⁽¹⁾
NO WRITE
1
2
t DS
t WFF
t CLK
t CLKH
tCLKL
t DH
DX
t WFF
(1)
t SKEW1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
1
2
t DS
t DH
t WFF
DX+1
t WFF
WEN
RCLK
REN
Q0 - Qn
t ENS
t ENH
tA
DATA IN OUTPUT REGISTER
t ENS
DATA READ
t ENH
tA
NEXT DATA READ
4675 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
RCLK
tENS
REN
EF
Q0 - Qn
OE
WCLK
WEN
D0 - Dn
tENH
tREF
1
NO OPERATION
tA
tOLZ
tOE
tSKEW3⁽¹⁾
LAST WORD
tENS
tENH
tDS
D0
tDHS
tCLKH
2
tCLK
NO OPERATION
tREF
tOHZ
tOLZ
tENS
tENH
tDS
tDH
D1
tCLKL
tENS
tENH
tA
LAST WORD
tENS
tENH
tREF
tA
D0
D1
4675 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17