DAC1201D125 Datasheet, PDF (17/26 Pages) NXP Semiconductors – Dual 12-bit DAC, up to 125 Msps

Integrated Device Technology
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.3 Timing
The DAC1201D125 can operate at an update rate up to 125 Msps. This generates an
input data rate of 125 MHz in Dual-port mode and 250 MHz in Interleaved mode. The
timing of the DAC1201D125 is shown in Figure 18.
DA11 to DA0/
DB11 to DB0
t_su(i)
t_h(i)
WRTA/
WRTB
t_w(WRT)
t_d(clk)
CLKA/
CLKB
t_w(CLK)
t_d
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
Fig 18. Timing of the DAC1201D125
10 %
90 %
t_t
t_s
001aaj117
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
• A configuration resulting in the same timing for the signals WRTA/WRTB and
CLKA/CLKB, can be achieved either by synchronizing them or by connecting them
together.
• The rising edge of the CLKA/CLKB signal can also be placed in a range from half a
period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns
after the rising edge of the WRTA/WRTB signal.
A typical set-up time of 0 ns and a hold time of 0.6 ns enables the DAC1201D125 to be
easily integrated into any application.
10.4 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
I_{Ofs} = I_IOUTP + I_IOUTN
(1)
The output current depends on the digital input data:
I_IOUTP
=
I_O

fs



D_---4--A_-0---9T---6-A_{--}
I_IOUTN
=
I
O

f
s



_---4_---0_---9_---5_--4--–_-0---9-D_--6---A_----T_---A_----_{-}
DAC1201D125 3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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