813N252I-09_15 Datasheet, PDF (17/23 Pages) Integrated Device Technology – VCXO Jitter Attenuator & FemtoClock Multiplier

813N252I-09 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 813N252I-09.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 813N252I-09 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 200mA = 693mW
• Power (outputs)_MAX = 31.55mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 31.55mW = 63.10mW
Total Power__MAX (3.3V, with all outputs switching) = 693mW + 63.10mW = 756.10mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.756W * 37°C/W = 113°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance _JA for 32 Lead VFQFN, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
1
32.4°C/W
2.5
29°C/W
©2015 Integrated Device Technology, Inc.
17
Revision C, December 10, 2015