5P49V5907 Datasheet, PDF (17/30 Pages) Integrated Device Technology – Programmable frequency

5P49V5907 DATASHEET
t6
Clock Jitter
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
differential outputs
46
ps
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
LVCMOS outputs
74
ps
RMS Phase Jitter (12kHz to 5MHz
integration range) reference clock (OUT0),
0.5
ps
25 MHz LVCMOS outputs
RMS Phase Jitter (12kHz to 20MHz
integration range) differential output, 25MHz
crystal, 156.25MHz output frequency
0.75
1.5
ps
t7
Output Skew between OUT1,
OUT2, OUT4
Skew between the same frequencies , with
outputs using the same driver format and
phase delay set to 0 ns.
75
ps
Output Skew between OUT3
and OUT5-11
Skew between outputs at same frequency
and conditions
49.5
PLL lock time from power-up, measured
84
ps
t8 ³ Startup Time
after all VDD's have raised above 90% of
their target value.
10
ms
t9 ⁴ Startup Time
PLL lock time from shutdown mode
2
ms
1. Practical low er frequency is determined by loop filter settings.
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/w rite time.
4. Actual PLL lock time depends on the loop configuration.
5. Duty Cycle is only guaranteed at max slew rate settings.
Table 21: PCI Express Jitter Specifications (V_DDO = 3.3V±5% or 2.5V±5%, T_A = -40°C to +85°C)
(For regular HCSL (OUT1, OUT2 and OUT4) outputs)
Symbol
Parameter
Conditions
Min
t_J (PCIe Gen1)
Phase Jitter
to-Peak
Peak-
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
t_{REFCLK_HF_RMS}
(PCIe Gen2)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input High
Band: 1.5MHz - Nyquist (clock
frequency/2)
Typ
30
2.56
Max
PCIe Industry
Specification Units Notes
86
ps
1,4
3.10
ps
2,4
t_{REFCLK_LF_RMS}
(PCIe Gen2)
Phase Jitter RMS
ƒ = 100MHz, 25MHz Crystal Input Low
Band: 10kHz - 1.5MHz
t_{REFCLK_RMS}
(PCIe Gen3)
ƒ = 100MHz, 25MHz Crystal Input
Phase Jitter RMS Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
0.27
0.8
3.0
ps
2,4
1.0
ps
3,4
Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained
transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.
2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation
band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS} (High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band).
3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is
subject to change pending the final release version of the specification.
4. This parameter is guaranteed by characterization. Not tested in production.
REVISION B 07/13/15
17
PROGRAMMABLE CLOCK GENERATOR