92HD99B Datasheet, PDF (16/225 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD99
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are
disabled. Per the HD Audio bus HDA015-B, the D3cold state is intended to be used just prior to
removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec
may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from
D3cold is less than 200mS.
2.9. Vendor Specific Function Group Power States D4/D5
The codec introduces vendor specific power states. A vendor defined verb is added to the Audio
Function Group that combines multiple vendor specific power control bits into logical power states
for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined
in the HD Audio specification and HDA015-B. The Vendor Specific D4 state provides lower digital
power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-
ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-
log power consumption by turning off all analog circuitry except for reset circuits.
States D4/D5 are not entered until D3cold has been requested so are actually D3cold options rather
than true, independent, power states. Software can pre-program the D4 or D5 state as a re-definition
of how the part will behave when the D3cold power state is requested or software may enter D3cold,
then set the D4 or D5 before performing the power state get command. The preferred method is to
request D3cold, then select D4 or D5 as desired.This will reduce the severity of pops encountered
when entering D4 or D5.
Both power states require a link reset or removal of DVDD to exit.
The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for
example) may take several seconds.
2.10. Low-voltage HDA Signaling
The codec is compatible with either 1.5V or 3.3V HDA bus signaling; in the 48QFN package the volt-
age selection is done dynamically based on the input voltage of DVDD_IO.
DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be
used for the HDA bus signals.
When in 1.5V mode, the codec can correctly decode BITCLK, SYNC, RESET# and SDO as they
operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as
they always function at their nominal voltage (DVDD or AVDD).
2.11. Multi-channel capture
The capability to assign multiple “ADC Converters” to the same stream is supported to meet the
microphone array requirements of Vista and future operating systems. Single converter streams are
still supported this is done by assigning unique non zero Stream IDs to each converter. All capture
devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restric-
tions regarding digital microphones.
The ADC Converters can be associated with a single stream as long the sample rate and the bits per
sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget
and is restricted to even values. The ADC converters will always put out a stereo sample and there-
fore require 2 channels per converter.
IDT CONFIDENTIAL
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92HD99