IDT72V3612 Datasheet, PDF (15/25 Pages) Integrated Device Technology – 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2

IDT72V3612 3.3V, CMOS SyncBiFIFO^TM
64 x 36 x 2
CLKB
tCLKH
tCLK
tCLKL
EFB HIGH
CSB
W/RB
MBB
ENB
B0 - B35
PGB,
ODD/
EVEN
tMDV
tEN
tENS2
tENH2
tA
Previous Data ⁽¹⁾
tPGS
tPGH
COMMERCIAL TEMPERATURE RANGE
tENS2
Word 1⁽¹⁾
tPGS
tENH2
tA
tPGH
tENS2
tENH2
No Operation
tDIS
Word 2⁽¹⁾
4659 drw 08
NOTE:
1. Read from FIFO1.
Figure 5. Port B Read Cycle Timing for FIFO1
CLKA
tCLKH
tCLK
tCLKL
EFA HIGH
CSA
W/RA
MBA
ENA
A0 - A35
PGA,
ODD/
EVEN
NOTE:
1. Read from FIFO2.
tENS2
tENH2
tMDV
tEN
tA
Previous Data ⁽¹⁾
tPGS
tPGH
tENS2
tENH2
Word 1⁽¹⁾
tPGS
tA
tPGH
Figure 6. Port A Read Cycle Timing for FIFO2
15
tENS2
tENH2
No Operation
tDIS
Word 2⁽¹⁾
4659 drw 09