IDT723611 Datasheet, PDF (15/20 Pages) Integrated Device Technology – CMOS SyncFIFO 64 x 36

IDT723611 CMOS SyncFIFO™
64 x 36
CLKA
ENA
tENS2
AF
[64-(X+1)] Words in FIFO
tENH2
tPAF
tSKEW2 ⁽¹⁾
1
(64-X) Words in FIFO
COMMERCIAL TEMPERATURE RANGES
2
tPAF
CLKB
ENB
tENS2
tENH2
3024 drw 10
Notes:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next
CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may
transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 7. Timing for AF when the FIFO is Almost Full
CLKA
CSA
W/RA
MBA
ENA
A0 - A35
tENS1
tENH1
tDS
tDH
W1
CLKB
tPMF
MBF1
tPMF
CSB
W/RB
MBB
tENS2
tENH2
ENB
tEN
tMDV
tPMR
tDIS
B0 - B35
W1 (Remains valid in Mail1 Register after read)
FIFO Output Register
Note:
1. Port-B parity generation off (PGB = L)
Figure 8. Timing for Mail1 Register and MBF1 Flag
3024 drw 11
15