IDT71V633 Datasheet, PDF (15/19 Pages) Integrated Device Technology – 64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect

IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Commercial and Industrial Temperature Ranges
ADDRESS
GW, BWE, BWx
CE, CS1
CS0
OE
DATAOUT
Av
Aw
Ax
Ay
(Av)
(Aw)
(Ax)
NOTES:
1 ZZ input is LOW, ADV is HIGH, and LBO is Don’t Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
Az
(Ay)
.
3780 drw 11
6.1452