IDT70V7399S Datasheet, PDF (15/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 128K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)⁽²⁾
tCYC2
tCH2
tCL2
CLK
CE0
CE1
UB/LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
ADDRESS⁽³⁾
An
tSA tHA
An +1
An + 2
An + 2
tSD tHD
An + 3
An + 4
DATAIN
(1)
tCD2
Dn + 2
tCKHZ
tCKLZ
tCD2
DATAOUT
Qn
Qn + 3
READ
NOP⁽⁴⁾
WRITE
READ
NOTES:
5630 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)⁽²⁾
tCYC2
tCH2
tCL2
CLK
CE0
CE1
UB/LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
(3)
ADDRESS
DATAIN
DATAOUT
An
tSA tHA
(1)
An +1
An + 2
tSD tHD
Dn + 2
tCD2
Qn ₍₄₎
tOHZ
An + 3
Dn + 3
An + 4
tCKLZ
An + 5
tCD2
Qn + 4
OE
NOTES:
READ
WRITE
READ
5630 drw 13
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.1452