IDT7005S Datasheet, PDF (15/20 Pages) Integrated Device Technology – HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING⁽¹⁾
ADDR"A"
CE"A"
tAS ⁽³⁾
tWC
INTERRUPT SET ADDRESS⁽²⁾
tWR ⁽⁴⁾
W R/ "A"
INT"B"
ADDR"B"
CE"B"
tINS ⁽³⁾
tAS(3)
tRC
INTERRUPT CLEAR ADDRESS⁽²⁾
2738 drw 17
OE"B"
INT"B"
tINR ⁽³⁾
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
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TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG^(1,4)
R/WL
L
X
X
X
Left Port
CEL OEL A12L-A0L INTL
L
X 1FFF X
X
X
X
X
X
X
X
L⁽³⁾
L
L
1FFE H⁽²⁾
R/WR
X
X
L
X
Right Port
CER OER A12R-A0R INTR
X
X
X
L⁽²⁾
L
L
1FFF H⁽³⁾
L
X 1FFE X
X
X
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
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6.06
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