IDT70V9369L_16 Datasheet, PDF (14/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)⁽¹⁾
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS
An
INTERNAL⁽³⁾
ADDRESS
ADS
An⁽⁷⁾
tSAD tHAD
An + 1
An + 2
An + 3
An + 4
CNTEN⁽⁷⁾
DATAIN
tSD tHD
Dn
Dn + 1
Dn + 1
Dn + 2
WRITE
EXTERNAL
ADDRESS
WRITE
WRITE
WITH COUNTERCOUNTER HOLD
Dn + 3
Dn + 4
WRITE WITH COUNTER
.
5648 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)⁽²⁾
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS⁽⁴⁾
An
An + 1
An + 2
INTERNAL⁽³⁾
ADDRESS
Ax⁽⁶⁾
R/W
0
tSW tHW
1
An
An + 1
ADS
CNTEN
CNTRST
DATAIN
tSRST tHRST
tSA tHAD
D
tSCN tHCN
tSD tHD
D0
DATAOUT⁽⁵⁾
Q0
Q1
Qn
(6)
COUNTER
RESET
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
.
READ
READ
ADDRESS n ADDRESS n+1
5648 drw 18
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The"InternalAddress"isequaltothe"ExternalAddress"whenADS =VIL andequalsthecounteroutputwhen ADS=VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Outputstate(High,Low,orHigh-impedance)isdeterminedbythepreviouscyclecontrolsignals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for
clarification.
7. CNTEN=VIL advancesInternalAddressfrom‘An’to‘An+1’.Thetransitionshownindicatesthetimerequiredforthecountertoadvance.
The ‘An +1’ Address is written to during this cycle.
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