MPC9772 Datasheet, PDF (13/17 Pages) Motorola, Inc – 3.3V 1:12 LVCMOS PLL Clock Generator

MPC9772 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9772
Output
Buffer
In
14
R_S = 36 
Z_O = 50 
MPC9772
Output
Buffer
In
14
R_S = 36 
Z_O = 50 
R_S = 36 
Z_O = 50
OutA
OutB0
OutB1
Figure 12. Single versus Dual Transmission Lines
The waveform plots in Figure 13 show the simulation
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9772 output buffer
is more than sufficient to drive 50  transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests the dual line driving
need not be used exclusively to maintain the tight
output-to-output skew of the MPC9772. The output waveform
in Figure 13 shows a step in the waveform, this step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36  series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
V_L = V_S (Z₀  (R_S+R₀ +Z₀))
Z₀ = 50 || 50
R_S = 36  || 36 
R₀ = 14
V_L = 3.0 (25  (18+17+25)
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
3.0
OutA
2.5
t_D = 3.8956
2.0
In
1.5
OutB
t_D = 3.9386
1.0
0.5
0
2
4
6
8
10
12
14
Time (ns)
Figure 13. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 14 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC9772
Output
Buffer
14
R_S = 22 
Z_O = 50 
R_S = 22 
Z_O = 50 
14  + 22  || 22  = 50  || 50 
25  = 25 
Figure 14. Optimized Dual Line Termination
Pulse
Generator
Z = 50
Z_O = 50
MPC9772 DUT
Z_O = 50
R_T = 50
V_TT
Figure 15. CCLK MPC9772 AC Test Reference
R_T = 50
V_TT
MPC9772 REVISION 7 JANUARY 8, 2013
13
©2013 Integrated Device Technology, Inc.