IDT72255 Datasheet, PDF (13/30 Pages) Integrated Device Technology – CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18

IDT72255/72265 SyncFIFO™
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty Flag (PAE) will go LOW
when the FIFO reaches the Almost-Empty condition as speci-
fied by the offset n stored in the Empty Offset register.
At the time of Master Reset, depending on the state of LD,
one of two possible default offset values are chosen. If LD is
LOW, then n = 07FH and the PAE switching threshold is 127
words from the Empty boundary, if LD is HIGH, then n = 3FFH
and the PAE switching threshold is 1023 words away from the
Empty boundary.
Any integral value of n from 0 to the maximum FIFO depth
minus 1 (8,191 words for the 72255, 16,383 words for the
72265) can be programmed into the Empty Offset register.
In IDT Standard Mode, if no reads are performed after
reset (MRS or PRS), the PAE will go HIGH after (n + 1) writes
to the IDT72255/72265.
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), the PAE will go HIGH after (n+2) writes to the
IDT72255/72265. In this case, the first word written to an
empty FIFO does not stay in memory, but goes unrequested
to the output register; therefore, it has no effect on determin-
ing the state of PAE.
Note that even though PAE is programmed to switch HIGH
during the first word latency period (tFWL), attempts to read
data will be ignored until EF goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAE is synchronous and updated on the rising edge of
RCLK. It is double-registered to enhance metastable immu-
nity.
HALF-FULL FLAG (HF)
This output indicates a half-full memory. The rising WCLK
edge that fills the memory beyond half-full sets HF LOW. The
flag remains LOW until the difference between the write and
read pointers becomes less than or equal to half of the total
depth of the device; the rising RCLK edge that accomplishes
this condition also sets HF HIGH.
In IDT Standard Mode, if no reads are performed after reset
(MRS or PRS), HF will go LOW after (D/2 + 1) writes, where D
is the maximum FIFO depth (8,192 words for the IDT72255,
16,384 words for the IDT72265).
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), HF will go LOW after (D/2+2) writes to the IDT72255/
72265. In this case, the first word written to an empty FIFO
does not stay in memory, but goes unrequested to the output
register; therefore, it has no effect on determining the state of
HF.
Because HF uses both RCLK and WCLK for synchroniza-
tion purposes, it is asynchronous.
DATA OUTPUTS (Q0-Q17)
Q0-Q17 are data outputs for 18-bit wide data.
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