IDT72251 Datasheet, PDF (13/17 Pages) Integrated Device Technology – CMOS SyncFIFOO 8192 X 9

IDT72251 CMOS SyncFIFO™
8192 x 9
tCLKH
WCLK
tCLKL
tENS
WEN1
(4)
tENH
WEN2
(If Applicable)
PAF
tENS
tENH
tPAF
(1)
Full - (m+1) words in FIFO
RCLK
COMMERCIAL TEMPERATURE RANGES
Full - m words in FIFO₍₂₎
tSKEW2 ⁽³⁾
tPAF
REN1,
REN2
tENS tENH
NOTES:
2655 drw 12
1. PAF offset = m.
2. 8192 - m words in FIFO IDT72251.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
5.14
13