IDT70V639S_15 Datasheet, PDF (13/24 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

IDT70V639S
High-Speed 3.3V 128K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
SEM/UB/LB⁽¹⁾
I/O
R/W
tAW
tWR
tEW
tDW
DATAIN VALID
tAS
tWP
tDH
tSOP
tACE
tOH
DATAOUT
VALID⁽²⁾
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
5621 drw 10
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate
UB/LB controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention^(1,3,4)
A0"A"-A2"A"
MATCH
SIDE⁽²⁾ "A"
R/W"A"
SEM"A"
A0"B"-A2"B"
SIDE⁽²⁾ "B"
R/W"B"
tSPS
MATCH
SEM"B"
5621 drw 11
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH. Refer also to Truth Table II for appropriate UB/LB controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
13