IDT70V3389S_14 Datasheet, PDF (13/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)⁽²⁾
tCYC2
tCH2
tCL2
CLK
CE0
CE1
UB, LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
(3)
ADDRESS
DATAIN
DATAOUT
An
tSA tHA
(1)
An +1
An + 2
tSD tHD
Dn + 2
tCD2
Qn ₍₄₎
tOHZ
An + 3
Dn + 3
An + 4
tCKLZ
An + 5
tCD2
Qn + 4
OE
NOTES:
READ
WRITE
READ
4832 drw 10
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Pipelined Read with Address Counter Advance⁽¹⁾
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS
An
ADS
tSAD tHAD
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT Qx - 1⁽²⁾
Qx
Qn
Qn + 1
Qn + 2⁽²⁾
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
NOTES:
4832 drw 11
1. CE0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.1432