IDT70P258_09 Datasheet, PDF (13/23 Pages) Integrated Device Technology – VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM

IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Industrial Temperature Range
70P258/248
Ind'l Only
Symbol
BUSY TIMING (M/S = VDD)
Parameter
Min. Max. Unit
tBAA
BUSY Access Time from Address Match
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
45
ns
tBAC
BUSY Access Time from Chip Enable LOW
____
45
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
____
45
ns
tAPS
Arbitration Priority Set-up Time⁽²⁾
5
____
ns
tBDD
BUSY Disable to Valid Data⁽³⁾
tWH
Write Hold After BUSY⁽⁵⁾
BUSY TIMING (M/S = VSS)
____
40
ns
35
____
ns
tWB
BUSY Input to Write⁽⁴⁾
tWH
Write Hold After BUSY⁽⁵⁾
0
____
ns
35
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay⁽¹⁾
____
80
ns
tDDD
Write Data Valid to Read Data Delay⁽¹⁾
____
65
ns
NOTES:
5675 tbl 13
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VDD)" or "Timing Waveform of Write
With Port-To-Port Delay (M/S = VSS)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
61.432