IDT7037 Datasheet, PDF (13/17 Pages) Integrated Device Technology – HIGH-SPEED 32K x 18 DUAL-PORT STATIC RAM

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing^(1,5)
tWC
ADDR"A"
CE"A"
INTERRUPT SET ADDRESS ⁽²⁾
tAS⁽³⁾
tWR ⁽⁴⁾
R/W"A"
INT"B"
ADDR"B"
CE"B"
tINS ⁽³⁾
tRC
INTERRUPT CLEAR ADDRESS ⁽²⁾
tAS⁽³⁾
4838 drw 15
OE"B"
INT"B"
tINR ⁽³⁾
4838 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV — Interrupt Flag^(1,4,5)
Left Port
R/WL
CEL
OEL
A14L-A0L
INTL
R/WR
CER
L
L
X
7FFF
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L⁽³⁾
L
L
X
L
L
7FFE
H⁽²⁾
X
X
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Chip Enable Truth Table.
Right Port
OER
A14R-A0R
X
X
L
7FFF
X
7FFE
X
X
INTR
Function
L⁽²⁾ Set Right INTR Flag
H⁽³⁾ Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
4838 tbl 16
61.432