932SQ426 Datasheet, PDF (13/25 Pages) Integrated Device Technology – 64-pin TSSOP and VFQFPN packages

932SQ426
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKINGS
Electrical Characteristics - PCI
T_A = 0 - 70°C; Supply Voltage V_DD/V_DDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
R_DSP
V_O = V_DD*(0.5)
Output High Voltage
V_OH
I_OH = -1 mA
Output Low Voltage
V_OL
I_OL = 1 mA
Output High Current
I_OH
MIN @V_OH = 1.0 V
MAX @V_OH = 3.135 V
Output Low Current
I_OL
MIN @V_OL = 1.95 V
MAX @ V_OL = 0.4 V
Clock High Time
T_HIGH
1.5V
Clock Low Time
T_LOW
1.5V
Edge Rate
t_slewr/f
Rising/Falling edge rate
Duty Cycle
d_t1
V_T = 1.5 V
Group Skew
t_skew
V_T = 1.5 V
Jitter, Cycle to cycle
t_jcyc-cyc
V_T = 1.5 V
See "Single-ended Test Loads Page" for termination circuits
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured between 0.8V and 2.0V}
Electrical Characteristics - 48MHz
T_A = 0 - 70°C; Supply Voltage V_DD/V_DDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
R_DSP
V_O = V_DD*(0.5)
Output High Voltage
V_OH
I_OH = -1 mA
Output Low Voltage
V_OL
Output High Current
I_OH
I_OL = 1 mA
MIN @V_OH = 1.0 V
MAX @V_OH = 3.135 V
Output Low Current
I_OL
MIN @V_OL = 1.95 V
MAX @ V_OL = 0.4 V
Clock High Time
T_HIGH
1.5V
Clock Low Time
T_LOW
1.5V
Edge Rate
t_{slewr/f_USB}
Rising/Falling edge rate
Duty Cycle
d_t1
V_T = 1.5 V
Jitter, Cycle to cycle
t_jcyc-cyc
V_T = 1.5 V
See "Single-ended Test Loads Page" for termination circuits
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured between 0.8V and 2.0V}
MIN
TYP
MAX UNITS NOTES
12
55
Ω
1
2.4
V
1
0.55
V
1
-33
mA
1
-33
mA
1
30
mA
1
38
mA
1
12
ns
1
12
ns
1
1
1.7
4
V/ns 1,2
45
51.3
55
%
1
279
500
ps
1
96
500
ps
1
MIN
TYP
MAX UNITS NOTES
20
60
Ω
1
2.4
V
1
0.55
V
1
-29
mA
1
-33
mA
1
29
mA
1
27
mA
1
8.094
10.036 ^ns
1
7.694
9.836
ns
1
1
1.8
2
V/ns 1,2
45
51
55
%
1
122
350
ps
1
IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKINGS
13
932SQ426
REV B 070815