IDT82V3389 Datasheet, PDF (121/156 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET

IDT82V3389 DATASHEET
SYNCHRONOUS ETHERNET WAN PLL
7.2.8 OUTPUT CONFIGURATION REGISTERS
OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration
Address: 6DH
Type: Read / Write
Default Value: 00001000
7
6
5
4
3
2
1
0
OUT1_PATH_S OUT1_PATH_S OUT1_PATH_S OUT1_PATH_S OUT1_DIVIDER OUT1_DIVIDER OUT1_DIVIDER OUT1_DIVIDER
EL3
EL2
EL1
EL0
3
2
1
0
Bit
Name
Description
These bits select an input to OUT1.
0000 ~ 0010: The output of T0 APLL. (default: 0000)
0011: T0 DPLL ETH path.
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
7-4
OUT1_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1010: The output of T4 APLL.
1011: T4 DPLL ETH path.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT1.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
3-0
OUT1_DIVIDER[3:0] (selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
Programming Information
121
June 13, 2012