IDT8N3S272 Datasheet, PDF (12/18 Pages) Integrated Device Technology – Fourth generation FemtoClock

IDT8N3S272 Data Sheet
LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
Schematic Layout
Figure 3 shows an example IDT8N3S272 application schematic. The
schematic example focuses on functional connections and is
intended as an example only and may not represent the exact user
configuration. Refer to the pin description and functional tables in the
datasheet to ensure the logic control inputs are properly set. For
example nOE can be configured from an FPGA instead of set with
pullup and pulldown resistors as shown.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter performance
isolation of the V_CC pin from power supply is required. In order to
achieve the best possible filtering, it is recommended that the
placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1µF
capacitor on the V_CC pin must be placed on the device side with direct
return to the ground plane though vias. The remaining filter
components can be on the opposite side of the PCB.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
Logic Control Input Examples
VCC
Set Logic
Input to '1'
VCC
Set Logic
Input to '0'
RU1
1K
To Logic
Input
pins
RD1
Not Install
RU2
Not Install
To Logic
Input
pins
RD2
1K
VCC
C4
10uF
3.3V
FB1
2
1
BLM18BB221SN1
C5
0.1uF
U1
1
6
DNU VCC
nOE
2
4
nOE Q
3
VEE
5
nQ
Place 0.1uF bypass cap
directly adjacent to
the VCC pin.
C3
0.1uF
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R2
R1
+3.3V PECL Receiv er
50
50
R3
50
For AC termination options consult the IDT Applications Note
"Termination - LVPECL"
Figure 3. IDT8N3S272 Schematic Example
IDT8N3S272CCD REVISION A NOVEMBER 28, 2012
12
©2012 Integrated Device Technology, Inc.