IDT70T3509M Datasheet, PDF (12/23 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70T3509M
High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Left Port Write to Pipelined Right Port Read^(1,2,4)
CLK"A"
R/W"A
"
ADDRESS"A"
DATAIN"A"
CLK"B"
R/W"B"
ADDRESS"B"
tSW tHW
tSA tHA
MATCH
tSD tHD
VALID
tCO⁽³⁾
tSW tHW
tSA tHA
MATCH
NO
MATCH
tCD2
NO
MATCH
DATAOUT"B"
VALID
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
,
tDC
5682 drw 09
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read^(1,2,4)
CLK "A"
tSW tHW
R/W "A"
ADDRESS "A"
tSA tHA
MATCH
tSD tHD
NO
MATCH
DATAIN "A"
VALID
CLK "B"
tCO⁽³⁾
R/W "B"
ADDRESS "B"
tSW tHW
tSA tHA
MATCH
tCD1
NO
MATCH
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
,
NOTES:
5682 drw 10
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
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