ICS83940DI_16 Datasheet, PDF (12/19 Pages) Integrated Device Technology – Low Skew, 1-to18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer

ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both differential signals must meet the V_PP and
V_CMR input requirements. Figures 2A to 2E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
Zo = 50Ω
CML Built-In Pullup
Zo = 50Ω
R1
100Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver
Figure 2B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84Ω
84Ω
Input
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
LVPECL
Input
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 2E. PCLK/nPCLK Input Driven by an SSTL Driver
ICS83940DYI REVISION C May 19, 2016
12
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