9SQL4952 Datasheet, PDF (12/20 Pages) Integrated Device Technology – 2-output CK420BQ Derivative

9SQL4952 DATASHEET
SMBus Table: Output Enable Register
Byte 0
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
X
Bit 6
Reserved
X
Bit 5
Reserved
X
Bit 4
Reserved
X
Bit 3
Reserved
X
Bit 2
BCLK OE1
Output Enable
RW
Low/Low
Enabled
1
Bit 1
BCLK OE0
Output Enable
RW
Low/Low
Enabled
1
Bit 0
Reserved
X
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default).
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Name
Control Function
Bit 7
SSENRB1
SS Enable Readback Bit1
Bit 6
SSENRB1
SS Enable Readback Bit0
Type
0
1
R 00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
Default
Latch
Latch
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
RW
SS control locked
Values in B1[4:3]
control SS amount.
0
Bit 4
SSENSW1
SS Enable Software Ctl Bit1 RW¹
00' = SS Off, '01' = -0.25% SS,
0
Bit 3
SSENSW0
SS Enable Software Ctl Bit0 RW¹
'10' = Reserved, '11'= -0.5% SS
0
Bit 2
Reserved
X
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude
RW
RW
00 = 0.6V
10 = 0.75V
01= 0.68V
11 = 0.85V
1
0
1. Spread must be selected OFF or ON with the hardware latch pin. These bits should not be used to turn spread ON or OFF after
power up. These bits can be used to change the spread amount, and B1[5] must be set to a 1 for these bits to have any effect on the
part. If These bits are used to turn spread OFF or ON, the system will need to be reset.
SMBus Table: BCLK Slew Rate Control Register
Byte 2
Name
Control Function
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
SLEWRATESEL BCLK1
Adjust Slew Rate of BCLK1
Bit 1
SLEWRATESEL BCLK0
Adjust Slew Rate of BCLK0
Bit 0
Reserved
Note: See "Low-Power HCSL Outputs" table for slew rates.
Type
RW
RW
0
Slow Setting
Slow Setting
1
Fast Setting
Fast Setting
Default
X
X
X
X
X
1
1
X
SMBus Table: REF Control Register
Byte 3
Name
Control Function
Type
0
Bit 7
Bit 6
REF
Slew Rate Control
RW
00 = Slowest
RW
10 = Fast
Bit 5
REF Power Down Function Wake-on-Lan Enable for REF RW
REF disabled in
Power Down
Bit 4
REF OE
REF Output Enable
RW
Disabled¹
Bit 3
Reserved
Bit 2
Bit 1
Reserved
Reserved
Bit 0
Reserved
1. The disabled state depends on Byte11[1:0]. '00' = Low, '01'=HiZ, '10'=Low, '11'=HIgh
1
01 = Slow
11 = Faster
REF runs in Power
Down
Enabled
Default
0
1
0
1
X
X
X
X
Byte 4 is Reserved
2-OUTPUT CK420BQ DERIVATIVE
12
DECEMBER 12, 2016