9FG830_17 Datasheet, PDF (12/19 Pages) Integrated Device Technology – Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
General SMBus serial interface information for the 9FG830
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC _(H)
• IDT clock will acknowledge
• Controller (host) sends the begining byte location = N
• IDT clock will acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC
(H)
• IDT clock will acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD _(H)
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N + X -1
• IDT clock sends Byte 0 through byte X (if X_(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host)
T
starT bit
IDT (Sla ve /Re ce ive r)
Slave Address DC_(H)
WR
W Rite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
P
stoP bit
ACK
Index Block Read Operation
Controlle r (Host)
T
starT bit
IDT (Sla ve /Re ce ive r)
Slave Address DC_(H)
WR
W Rite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address DD_(H)
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N
Not acknowledge
P
stoP bit
Byte N + X - 1
IDT^® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
12
1680E—04/04/17