830154I-08 Datasheet, PDF (12/17 Pages) Integrated Device Technology – Over-Voltage Tolerant 1.5V, 1:4 Fanout Buffer

830154I-08 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 830154I-08.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the830154I-08 is the sum of the core power plus the power dissipation in the load(s). The following is the power
dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)_MAX = V_{DD_MAX} * I_{DD_MAX} = 3.465V *1mA = 3.465mW
Total Static Power:
= Power (core)_MAX = 3.465mW
Dynamic Power Dissipation at F_{OUT_MAX} (160MHz)
Total Power (160MHz) = [(C_PD * N) * Frequency * (V_DDO)²] = [(14pF *4) * 160MHz * (3.465V)²] = 107.6mW
N = number of outputs
Total Power
= Static Power + Dynamic Power Dissipation
= 3.465mW + 107.6mW
= 111.065mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 121.5°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.111W *121.5°C/W = 98.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance _JA for 8 Lead TSSOP, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
121.5°C/W
1
117.3°C/W
2.5
115.3°C/W
Table 6B. Thermal Resistance _JA for 8 Lead SOIC, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
103°C/W
1
94°C/W
2.5
89°C/W
©2016 Integrated Device Technology, Inc
12
Revision A March 30, 2016