IDT82P2281 Datasheet, PDF(113/375 Page) Integrated Device Technology – Single T1/E1/J1 Long Haul Short Haul Transceiver

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IDT82P2281 Datasheet, PDF (113/375 Pages) Integrated Device Technology – Single T1/E1/J1 Long Haul Short Haul Transceiver

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IDT82P2281

5.1.1.2

PMON

Indirect Register

SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Address (Hex)

00

01

02

03

04

05

06

07

08

09

0A

0B

Bit 7

CRCE7

-

FER7

-

-

-

PRGD7

PRGD15

LCV7

LCV15

DDSE7

-

Bit 6

CRCE6

-

FER6

-

-

-

PRGD6

PRGD14

LCV6

LCV14

DDSE6

-

Bit 5

CRCE5

-

FER5

-

-

-

PRGD5

PRGD13

LCV5

LCV13

DDSE5

-

Bit 4

CRCE4

-

FER4

-

-

OOF4

PRGD4

PRGD12

LCV4

LCV12

DDSE4

-

Bit 3

CRCE3

-

FER3

FER11

-

OOF3

PRGD3

PRGD11

LCV3

LCV11

DDSE3

-

Bit 2

CRCE2

-

FER2

FER10

COFA2

OOF2

PRGD2

PRGD10

LCV2

LCV10

DDSE2

-

Bit 1

CRCE1

CRCE9

FER1

FER9

COFA1

OOF1

PRGD1

PRGD9

LCV1

LCV9

DDSE1

DDSE9

Bit 0

CRCE0

CRCE8

FER0

FER8

COFA0

OOF0

PRGD0

PRGD8

LCV0

LCV8

DDSE0

DDSE8

Register

CRCE Counter Mapping 0

CRCE Counter Mapping 1

FER Counter Mapping 0

FER Counter Mapping 1

COFA Counter Mapping

OOF Counter Mapping

PRGD Counter Mapping 0

PRGD Counter Mapping 1

LCV Counter Mapping 0

LCV Counter Mapping 1

DDSE Counter Mapping 0

DDSE Counter Mapping 1

Reference Page

P 210

P 210

P 211

P 211

P 212

P 212

P 213

P 213

P 214

P 214

P 215

P 215

RCRB

Address (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register

Reference Page

01 ~ 18

-

-

- EXTRACT A

B

C

D

Extracted Signaling Data/Extract

P 216

Enable Register for CH1 ~ CH24

RPLC

Address (Hex) Bit 7 Bit 6 Bit 5 Bit 4

01 ~ 18 SUBST2 SUBST1 SUBST0 SINV

Bit 3

OINV

21 ~ 38

DTRK7 DTRK6 DTRK5 DTRK4 DTRK3

41 ~ 58

-

TEST

- STRKEN A

Bit 2

EINV

DTRK2

B

Bit 1

G56K

DTRK1

C

Bit 0

Register

Reference Page

GAP Channel Control Register for CH1

~ CH24

DTRK0 Data Trunk Conditioning Code

Register for CH1 ~ CH24

D Signaling Trunk Conditioning Code

Register for CH1 ~ CH24

P 217

P 218

P 219

TPLC

Address (Hex) Bit 7

01 ~ 18 SUBST2

21 ~ 38

DTRK7

41 ~ 58

-

Bit 6

SUBST1

DTRK6

TEST

Bit 5 Bit 4

SUBST0 SINV

Bit 3

OINV

DTRK5 DTRK4 DTRK3

SIGINS STRKEN A

Bit 2

EINV

DTRK2

B

Bit 1

G56K

DTRK1

C

Bit 0

Register

Reference Page

GAP

DTRK0

D

Channel Control Register for CH1

~ CH24

Data Trunk Conditioning Code

Register for CH1 ~ CH24

Signaling Trunk Conditioning

Code Register for CH1 ~ CH24

P 220

P 221

P 222

Programming Information

102

October 7, 2003

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