IDT72801_13 Datasheet, PDF (11/16 Pages) Integrated Device Technology – DUAL CMOS SyncFIFO

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO^TM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLKA
(WCLKB)
DA0 - DA8
(DB0 - DB8)
FFA (FFB)
WENA1
(WENB1)
WENA2
(WENB2)
(If Applicable)
NO WRITE
tSKEW1
tDS
tWFF
tENS
tENS
tDH
tWFF
tENH
tENH
NO WRITE
tSKEW1
NO WRITE
tWFF
tENS⁽¹⁾
tENS⁽¹⁾
RCLKA
(RCLKB)
tENS
RENA1
(RENB2)
OEA LOW
(OEB)
tENH
tA
QA0 - QA8
(QB0 - QB8)
DATA IN OUTPUT REGISTER
tENS
tENH
tA
DATA READ
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
NEXT DATA READ
3034 drw 09
WCLKA (WCLKB)
tDS
DA0 - DA8
(DB0 - DB8)
tENS
WENA1, (WENB1)
tENS
DATA WRITE 1
tENH
tENH
WENA2 (WENB2)
(If Applicable)
RCLKA (RLCKB)
tSKEW1
(1)
tFRL
tREF
EFA (EFB)
tDS
tENS
DATA WRITE 2
tENH
tENS
tENH
tSKEW1
tFRL(1)
tREF
tREF
RENA1, RENA2
(RENB1, RENB2)
OEA (OEB) LOW
QA0-QA8
(QB0-QB8)
tA
DATA IN OUTPUT REGISTER
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 9. Empty Flag Timing
11
DATA READ
3034 drw 10
MARCH 2013