ICS854S006AGILF Datasheet, PDF (11/15 Pages) Integrated Device Technology – Low Skew, 1-to-6, Differential-to- LVDS Fanout Buffer

ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS854S006I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S006I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
DD
• Power (core) = V * I = 3.465V * 55mA = 190.575mW
MAX
DD_MAX
DD_MAX
• Power (outputs) = V
*I
= 3.465V * 105mA = 363.825mW
MAX
DDO_MAX DDO_MAX
Total Power = 190.575mW + 363.825mW = 554.4mW
_MAX
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C
ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows:
Tj
=
θ_JA
*
Pd_total
+
T
A
Tj = Junction Temperature
θ = Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used.
Assuming no air flow and a multi-layer board, the appropriate value is 70°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 70°C/W = 123.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 24-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
70°C/W
1
65°C/W
2.5
62°C/W
ICS854S006AGI REVISION B JANUARY 18, 2010
11
©2010 Integrated Device Technology, Inc.