ICS8530I-01 Datasheet, PDF (11/18 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

ICS8530DYI-01 Data Sheet
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 4A and
4B show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it would be
recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
3.3V
Z_o = 50Ω
3.3V
+
LVPECL
Z_o = 50Ω
R1
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
* Z_o
_
Input
R2
50Ω
V_CC - 2V
RTT
Figure 4A. 3.3V LVPECL Output Termination
3.3V
LVPECL
3.3V
R3
R4
125Ω
125Ω
3.3V
Z_o = 50Ω
+
Z_o = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 4B. 3.3V LVPECL Output Termination
ICS8530DYI-01 REVISION A FEBRUARY 22, 2011
11
©2011 Integrated Device Technology, Inc.