ICS844251-14 Datasheet, PDF (11/16 Pages) Integrated Device Technology – FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR

ICS844251-14
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Schematic Example
Figure 5 shows an example of ICS844251-14 application
schematic. In this example, the device is operated at V_DD = 3.3V.
The decoupling capacitor should be located as close as possible
to the power pin. The 18pF parallel resonant 25MHz crystal is
used. The C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. For different board layouts, the C1 and C2
may be slightly adjusted for optimizing frequency accuracy. For the
LVDS output drivers, place a 100Ω resistor as close to the receiver
as possible.
VDD
VDD R1
10
C3
0.1u
VDDA
C4
10u
C1
27pF
2₁ 5_{8 p}M_F Hz
X1
C5
0.01u
U1
1
2
VDDA
3
4
GND
XTAL_OUT
XTAL_IN
VDD
8
7
Q
nQ
FREQ_SEL
6
5
FREQ_SEL
Zo = 50 Ohm
Q
R2
+
100
Zo = 50 Ohm
-
nQ
C2
27pF
Logic Input Pin Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
Zo = 50 Ohm
Q
R3
50
+
C7
0.1uF
-
R4
Zo = 50 Ohm
50
nQ
Alternate
LVDS
Termination
Figure 5. ICS844251-14 Schematic Example
IDT™ / ICS™ LVDS CLOCK GENERATOR
11
ICS844251BG-14 REV. A MAY 1, 2009