9DBU0231 Datasheet, PDF (11/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0231 DATASHEET
SMBus Table: Output Enable Register ¹
Byte 0
Name
Control Function
Type
0
Bit 7
Reserved
Bit 6
Reserved
Bit 5
DIF OE1
Output Enable
RW
Low/Low
Bit 4
Reserved
Bit 3
DIF OE0
Output Enable
RW
Low/Low
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Reserved
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
1
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Bit 7
Bit 6
Name
PLLMODERB1
PLLMODERB0
Control Function
PLL Mode Readback Bit 1
PLL Mode Readback Bit 0
Type
R
R
Bit 5
PLLMODE_SWCNTRL Enable SW control of PLL Mode RW
Bit 4
PLLMODE1
PLL Mode Control Bit 1
Bit 3
PLLMODE0
PLL Mode Control Bit 0
Bit 2
Reserved
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
RW¹
RW¹
RW
RW
0
1
See PLL Operating Mode Table
Values in B1[7:6] Values in B1[4:3]
set PLL Mode
set PLL Mode
See PLL Operating Mode Table
00 = 0.55V
10= 0.75V
01 = 0.65V
11 = 0.85V
Default
Latch
Latch
0
0
0
1
1
0
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Control Function
Reserved
Reserved
Slew Rate Selection
Reserved
Slew Rate Selection
Reserved
Reserved
Reserved
Type
RW
RW
0
Slow Setting
Slow Setting
1
Fast Setting
Fast Setting
Default
1
1
1
1
1
1
1
1
SMBus Table: FB Slew Rate Control Register
Byte 3
Bit 7
Bit 6
Bit 5
Bit 4
Name
Control Function
Reserved
Reserved
Reserved
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
Reserved
Reserved
Reserved
Adjust Slew Rate of FB
Type
RW
0
Slow Setting
1
Fast Setting
Default
1
1
0
0
0
1
1
1
Byte 4 is Reserved and reads back 'hFF
REVISION D 04/22/15
11
2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB