9DBL0841 Datasheet, PDF (11/19 Pages) Integrated Device Technology – 8-output 3.3V PCIe Zero-Delay Buffer

9DBL0841 / 9DBL0851 DATASHEET
SMBus Table: Output Enable Register ¹
Byte 0
Name
Control Function
Type
0
1
Default
Bit 7
DIF OE7
Output Enable
RW
Pin Control
1
Bit 6
DIF OE6
Output Enable
RW
Pin Control
1
Bit 5
DIF OE5
Output Enable
RW
Pin Control
1
Bit 4
Bit 3
DIF OE4
DIF OE3
Output Enable
Output Enable
RW
RW
See B11[1:0]
Pin Control
Pin Control
1
1
Bit 2
DIF OE2
Output Enable
RW
Pin Control
1
Bit 1
DIF OE1
Output Enable
RW
Pin Control
1
Bit 0
DIF OE0
Output Enable
RW
Pin Control
1
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
0
1
Bit 7
Bit 6
PLLMODERB1
PLLMODERB0
PLL Mode Readback Bit 1
R
PLL Mode Readback Bit 0
R
See PLL Operating Mode Table
Bit 5
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
Bit 4
Bit 3
PLLMODE1
PLLMODE0
PLL Mode Control Bit 1
PLL Mode Control Bit 0
RW¹
RW¹
See PLL Operating Mode Table
Bit 2
Reserved
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude
RW
RW
00 = 0.6V
10 = 0.75V
01= 0.68V
11 = 0.85V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
Default
Latch
Latch
0
0
0
1
1
0
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Bit 7
SLEWRATESEL DIF7
Adjust Slew Rate of DIF7
Bit 6
SLEWRATESEL DIF6
Adjust Slew Rate of DIF6
Bit 5
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
Bit 4
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
Bit 3
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
Bit 2
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 1
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 0
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Note: See "Low-Power HCSL Outputs" table for slew rates.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
1
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Default
1
1
1
1
1
1
1
1
SMBus Table: Frequency Select Control Register
Byte 3
Name
Control Function
Bit 7
Reserved
Bit 6
Bit 5
FREQ_SEL_EN
Reserved
Enable SW selection of
frequency
Bit 4
FSEL1
Freq. Select Bit 1
Bit 3
FSEL0
Freq. Select Bit 0
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
Reserved
Reserved
Adjust Slew Rate of FB
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Type
RW
RW¹
RW¹
RW
0
1
SW frequency
SW frequency
change disabled change enabled
00 = 100M, 10 = 125M
01 = 50M, 11= Reserved
Slow Setting
Fast Setting
Default
1
1
0
0
0
1
1
1
Byte 4 is Reserved
FEBRUARY 9, 2017
11
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER