844201 Datasheet, PDF (11/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

ICS844201-45 Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS CLOCK GENERATOR
Schematic Example
Figure 4 shows an example of ICS844201-45 application schematic.
In this example, the device is operated at V_DD = 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 =
27pF are recommended for frequency accuracy. For different board
layouts, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. Two examples of LVDS for receiver without
built-in termination are shown in this schematic.
C2
27pF
2₁ 5_{8 p}M_F Hz
X1
XTAL_OUT
XTAL_IN
FSEL
C1
27pF
U1
1
2
3
4
GND
XTAL_OUT
XTAL_IN
FSEL
Logic Input Pin Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
Q
nQ
VDD
nc
8
7
6
5
VDD
Zo = 50 Ohm
Q
R1
+
100
Zo = 50 Ohm
-
nQ
C3
0.01u
VDD=3.3V
Zo = 50 Ohm
Q
R3
50
+
C9
0.1uF
-
R4
Zo = 50 Ohm
50
nQ
Alternate
LVDS
Termination
Figure 4. ICS844201-45 Schematic Example
ICS844201BG-45 REVISION A OCTOBER 1, 2013
11
©2013 Integrated Device Technology, Inc.